Static CMOS is the logic style used in almost every digital chip. Each gate has two networks. The pull-down network of NMOS transistors connects the output to ground, and the pull-up network of PMOS transistors connects it to VDD. For every input combination exactly one of them conducts, so the output is always driven and no static current flows.
From expression to network
- Write the function the pull-down network must implement. The gate's output is its complement, so for Y = !(a·b + c) the pull-down implements a·b + c.
- An AND of terms becomes NMOS transistors in series: all must be on to conduct.
- An OR becomes parallel branches: any one conducting is enough.
- The pull-up network is the dual: series becomes parallel and parallel becomes series, with PMOS transistors driven by the same inputs.
The result for !(a·b + c) is the AOI21 gate: a and b in series parallel with c at the bottom, a parallel to b in series with c at the top, 6 transistors in all.
How the minimizer works
Turn on Minimize first and the tool works the way you would by hand, then goes further. It reads the truth table (you can also type minterms such as m(1,3,7,11,15) + d(0,2,5), with don't cares), draws the Karnaugh map, lists the prime implicants with Quine–McCluskey and marks the essential ones. It then factors the result: shared literals and shared sub-expressions are pulled out, so ac + ad + bc + bd becomes (a + b)(c + d), 4 literals instead of 8. Finally it builds every form (SOP, POS, factored, and the complement as one inverting stage), counts transistors including input inverters, and keeps the cheapest.
Non-inverting functions
One static stage always inverts. To build Y = a·b, build NAND2 and add an inverter: 4 + 2 = 6 transistors. An expression that needs a complemented input, such as a·!b, also needs an inverter on b unless !b is already available.
Sizing and logical effort
Transistors in series add resistance. To match the drive of a reference inverter (NMOS width 1, PMOS width 2), make each transistor as wide as the series stack it sits in: NAND2 uses NMOS of width 2 and PMOS of width 2. The logical effort g = input capacitance ÷ inverter input capacitance says how much harder the gate is to drive a load with: inverter 1, NAND2 4/3, NOR2 5/3. NOR gates have long PMOS stacks, which is why designers prefer NAND-based logic.
Worked example
The full-adder carry Cout = a·b + a·cin + b·cin needs a 12-transistor complex gate plus an inverter. Written as the mirror adder !(a·b + cin·(a + b)), it needs only 10 transistors and gives the inverted carry, which the next stage can use directly.
